Method for reducing memory consumption when carrying out edge enhancement in multiple beam pixel apparatus

ABSTRACT

A method for reducing memory consumption when carrying out edge enhancement in a multiple beam pixel apparatus is provided, wherein Static Random Access Memories and first in first out buffers are employed. When the first to the n th  input units read the next bit data, the first rows of the bit data in the first to the n th  buffers are removed, and each row of bit data behind the first rows is moved towards left by one bit. The first rows of bit data in the (n+1) th  to the (n+4) th  buffers are stored in one end of the first to the fourth memories respectively, and a bit data is taken out from the other end of each of the memories, to be sequentially stored in the end of the first to the fourth buffers, and the read next bit data is stored in the fifth to the (n+4) th  buffers.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method for reducing memoryconsumption when carrying out Edge Enhancement in a multiple beam pixelapparatus. More particularly, the present invention relates to a methodfor reducing the consumption of hardware resources when carrying outmultiple groups of Edge Enhancement operations.

2. Related Art

Recently, in the field of image processing, the key point of mostresearch and development is to improve the visual effect of an imageoutput apparatus (e.g. a printer) such that the visual effect generatedafter image output matches with the real subject. The edge of theoriginal image object, e.g., texts, curves, three-dimensional objects,etc., can be approximated by the linear equation or natural logarithm,etc., to be more smooth. When these objects are digitally processed,they are required to be converted into a matrix form which isprocessable for an image output apparatus, and their edges are requiredto match the grids of the apparatus.

However, if the resolution of the image output apparatus is relativelylow, the edge of the image object is found to be step-shaped of one gridby another grid through the naked eye, and a smooth edge as that of theoriginal image object cannot be obtained. Therefore, various solutionsare proposed to reduce the jagged effect on the edge of the imageobject, such that the image output by the image output apparatus canmatch with the real subject.

As for Edge Enhancement Method and Apparatus for Dot Matrix Devicesdisclosed in U.S. Pat. No. 5,029,108, the dotting state of the pixels ofan image edge and that of the surrounding pixels are compared with aplurality of predetermined pictures, to determine which predeterminedpicture the pixels of the image edge match with, thus it is determinedhow to dot the pixels at the image edge to smooth the output image edgeand to allow the image more accurately match with the original one. Theenhancement of central pixels of each predetermined picture will bemodified differently according to the dotting state of the surroundedpixels, for example, dotting at ¼ to the left of the central pixel,dotting at ⅔ to the right of the central pixels, etc.

Referring to FIG. 1, it is a structural schematic view of a conventionalone beam Edge Enhancement Technology (EET) application. The serial datais read sequentially by an input unit 140 with the unit of one bit, andthen after being processed by a one beam EET 10, the image is output toa display screen through a laser diode (LD) and a spinner, or printed bya printer, such that the edge of the output image is relatively smooth,without jagged edges.

Referring to FIG. 2, it is a schematic view of the operation of theconventional one beam EET 10. The serial data is stored in the fifthbuffer of a first in first out (FIFO) buffer 120 after being read by aninput unit 140, and a 9×5 table 110 can be taken out from the serialdata in the FIFO buffer 120 through registering by a Static RandomAccess Memory (SRAM) 170. And the central pixel 130 of the table isdetected to be a To Be Adjusted Pixel (TBAP) or not, and if it is, theTBAP is adjusted through the one beam EET 10.

Referring to FIG. 3, it is a structural schematic view of a conventionaltwo-beam engine application. The serial data in FIG. 3 should be dividedinto odd column of serial data read by the first input unit 141, andeven column of serial data read by the second input unit 142sequentially, thus double speed can be achieved compared with theoriginal one beam engine output. If the one beam EET 10 is furtheremployed individually, the edge smoothness of the output image can beimproved. Especially, since the EET carried out for the TBAP is at aslow speed, the output speed will be significantly improved, if doubleoutput speed is achieved.

However, in the Edge Enhancement operation, the serial data must be readin sequence, therefore the first input unit 141 and the second inputunit 142 cannot be accessed at random. Instead, they must read therespective data to be processed respectively, thus a double sized FIFObuffer 120 and a SRAM 170 are required. This is equivalent to repeatedlyreading data twice from the external, result in a mass consumption ofthe memory capacity used for operation in the internal of the system,especially the bandwidth used by the internal signal transmission bus,and the Central Processing Unit (CPU) resources consumed whentransmitting data. No matter the Edge Enhancement is carried out to oddcolumn of serial data or to even column of serial data, the data must beread repeatedly for many times to construct an individual 9×5 table 110.As a result, other processing procedures are significantly influenced.Although the printing speed is increased and output effects areimproved, relative larger hardware costs are required, especially in theconsumption of memory and CPU resources.

SUMMARY OF THE INVENTION

In view of the above problems, the object of the present invention is toprovide a method for reducing memory consumption when carrying out EdgeEnhancement in a multiple beam pixel apparatus, wherein when reading theserial data, the serial data are sequentially moved in FIFO buffer andStatic Random Access Memory (SRAM), and n 9×5 tables can be taken outfrom the first in first out (FIFO) buffer to act as the tables requiredfor Edge Enhancement Technology (EET) operation.

Accordingly, in order to achieve the above objects, the method forreducing memory consumption when carrying out Edge Enhancement in amultiple beam pixel apparatus disclosed in the present inventioncomprises the following steps:

Firstly, the first column of serial data is read by the first inputunit, and the second column of serial data is read by the second inputunit, and similarly, the n^(th) column of serial data is read by then^(th) input unit. The first 9 rows of data of the first buffer to the(n+4)^(th) buffer are filled according to the order of each column ofserial data, and the serial data in the first 4 columns without beingstored in the buffer are temporarily stored in the SRAM.

Meanwhile, in the (n+4) buffers, n 9×5 tables are taken out sequentiallyfor detecting the central pixel of the individual table to be a To BeAdjusted Pixel (TBAP) or not.

If it is a TBAP, the Edge Enhancement operation is carried out at the9×5 table with the TBAP as the central pixel to generate an adjustedcentral pixel value.

Then, the n central pixel values, being or without being adjusted, areoutput.

When the first input unit to the n^(th) input unit continue to read thenext bit data, the first rows of bit data of the first buffer to then^(th) buffer are removed, and the first rows of bit data of the(n+1)^(th) buffer to the (n+4)^(th) buffer are stored in one end of thefirst memory to the fourth memory respectively. Each row of bit databehind the first row of the FIFO buffer is moved towards left by onebit, and one bit data is taken out from the other ends of each of thefour RAMs, and it is sequentially stored in the row at the end of thefirst buffer to the fourth buffer, and the next bit data read by thefirst input unit to the n^(th) input unit are stored in the fifth bufferto the (n+4)^(th) buffer.

And finally, the central pixel value of each 9×5 table is detected andadjusted according to the above steps, until there is no next bit datato be input.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given herein below for illustration only for, andthus are not limitative of the present invention, and wherein:

FIG. 1 is a structural schematic view of a conventional one beam EdgeEnhancement Technology (EET) application;

FIG. 2 is an operational schematic view of the conventional one beamEET;

FIG. 3 is a structural schematic view of a conventional two-beam engineapplication;

FIG. 4 is a structural schematic view of a two-beam EET according to thepresent invention;

FIG. 5 a to 5 i is exploded schematic views of a processing flow of anembodiment of the two-beam EET according to the present invention;

FIG. 6 is a schematic view of an embodiment of taking out a 9×5 tablerequired by the two-beam EET according to the present invention;

FIGS. 7 a and 7 b are schematic views of an embodiment of transformingfrom an original operation block to the next operation block in thetwo-beam EET according to the present invention;

FIG. 8 is a schematic view of carrying out Edge Enhancement with themultiple beam pixel apparatus according to the present invention;

FIG. 9 is a flow chart of a method of the present invention; and

FIG. 10 is a flow chart of a method for transforming from an originaloperation block to the next operation block according to the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

A method for reducing memory consumption when carrying out EdgeEnhancement in a multiple beam pixel apparatus is disclosed. In thefollowing detailed descriptions of the present invention, variousspecific details will be provided to completely illustrate the presentinvention. However, it will be appreciated by those skilled in the art,the present invention can be implemented without using the specificdetails, or be implemented with alternative elements or methods. Inother cases, the known methods, procedures, parts, and circuits will notbe described in great detail, to avoid undesirably confusing the keypoint of the present invention.

Although the present invention can be extended to the application of noutput pixel apparatuses, to be easily understood, two output pixelapparatuses are taken as the embodiment for illustration. Referring toFIG. 4, it is a structural schematic view of a two-beam Edge EnhancementTechnology (EET) according to the present invention, wherein the firstinput unit 141 is used for reading the odd column of serial data,whereas the second input unit 142 is used for reading the even column ofserial data; after being read, the serial data are processed by atwo-beam EET 20, and then they are sent to the odd columns of LaserDiodes (LD) and even columns of LDs respectively; then two columns ofserial data are output to a display apparatus or a printing apparatusthrough a spinner. In the present invention, two one-beam EETs 10 arealso employed to carry out the two-beam EET 20, but only six first infirst out (FIFO) buffers 120 and Static Random Access Memories (SRAM)170 are required, being only half of that of the conventional art. Moredetailed method for processing data is shown in the following drawings.

Referring to FIG. 5 a, at first, six buffers in a FIFO buffer 120 areturned on, wherein the FIFO buffer 120 is generally a register connectedto CPU with a faster accessing speed than that of SRAM 170, but it isrelatively expensive, with smaller capacity, about less than 1K bytes.The first input unit 141 reads the first bit data of the first column ofserial data (assumed to be “0” in the figures), and meanwhile the secondinput unit 142 reads the first bit data of the second column of serialdata (assumed to be “1” in the figures). After being read, the bit dataare stored in the fifth buffer and the sixth buffer at the back end of aspace block 160, wherein the space block 160 is used for spacing anoperation block 180 with a register block 150, and in practice the spaceblock 160 can be omitted to save the space of the register.

Next, the first input unit 141 continues to read the second bit data ofthe first column of serial data, which is also stored in the originalposition for storing the first bit data, while the first bit data ismoved left by one bit. The same procedure is repeated on the secondinput unit 142. As shown in FIG. 5 b, in case of the first bit data(“0”) of the first column of serial data and the second bit data (“1”)of the second column of serial data being moved to the first rows of thefifth buffer and the sixth buffer, when the next bit data is read, thefirst bit data (“0”) of the first column of serial data is moved to oneend of the third memory to be written, meanwhile the second bit data(“1”) of the second column of serial data is also moved to the same endof the fourth memory to be written.

Then, the serial data are continued to be read. “0” and “1” are moved tothe other ends of the third memory and the fourth memory, as shown inFIG. 5 c. And then the two bit data “0” and “1” will be move to the backend of the register block 150 of the third buffer and the fourth bufferto be stored, wherein the space of the register block 150 can be set asrequired by the practical operation. After the first column of serialdata and the second column of serial data are all read by the FIFObuffer 120 and the SRAM 170, referring to FIG. 5d, when the first bitdata (“0”) of the first column of serial data and the second bit data(“1”) of the second column of serial data are moved to the first rows ofthe third buffer and the fourth buffer beginning from the back of thespace block 160, the first input unit 141 reads the first bit data(assumed as “2” in the figures) of the third column of serial data, andmeanwhile the second input unit 142 also reads the first bit data(assumed as “3” in the figures) of the fourth column of serial data. Andthen they are temporarily stored in the fifth buffer and the sixthbuffer at the back end of the space block 160 by the same way of storing0 and 1.

However, in practice, the space block 160 and register block 150 alsocan be omitted in the register, thus the space occupied by the registerwhen carrying out the EET operation is further reduced, butcorrespondingly the efficiency of data processing will be much lowerunder the configuration without the register mechanism. It is carriedout as shown in FIG. 5 e, wherein when the first bit data (“0”) of thefirst column of serial data and the second bit data (“1”) of the secondcolumn of serial data are ready to be moved to the ninth row of anoperation block 180 of the third buffer and the fourth buffer, the firstinput unit 141 and the second input unit 142 will also read the firstbit data (assumed as “2” in the figures) of the third column of serialdata and the first bit data (assumed as “3” in the figures) of thefourth column of serial data at the same time. “0”, “1”, “2”, and “3”are written meanwhile in the ninth rows of the third buffer, the fourthbuffer, the fifth buffer, and the sixth buffer of the operation block120. When the first input unit 141 and the second input unit 142continue to read the second bit data of the third column of serial dataand the fourth column of serial data, the four first bit data “0”, “1”,“2”, and “3” will be moved to the eighth row from the ninth row. Then,the second bit data of the first column of serial data, the secondcolumn of serial data, the third column of serial data, and the fourthcolumn of serial data are written in the ninth rows of the third buffer,the fourth buffer, the fifth buffer, and the sixth buffer.

Back to the illustration of the embodiment comprising the space block160 and the register block 150, referring to FIG. 5 f, in case of “0”,“1”, “2”, and “3” being moved to the first rows of the third buffer, thefourth buffer, the fifth buffer, and the sixth buffer, when the firstinput unit 141 and the second input unit 142 continue to read the nextbit data, “0”, “1”, “2”, and “3” are meanwhile moved to one end of thefirst memory, the second memory, the third memory, and the fourth memoryto be written.

When the first column of serial data, the second column of serial data,the third column of serial data, and the fourth of column serial datacompletely fill the SRAM 170 according to the order of pointer, that is,“0”, “1”, “2”, and “3” have reached the other end of the SRAM 170 due tobeing moved. As shown in FIG. 5 g, “0”, “1”, “2”, and “3” will be movedto the register block 150 of the first buffer, the second buffer, thethird buffer, and the fourth buffer. After the first column of serialdata, the second column of serial data, the third column of serial data,and the fourth column of serial data are all read by the FIFO buffer 120and the SRAM 170, referring to FIG. 5 h, at this time, “0”, “1”, “2”,and “3” have been moved to the first row of the first buffer, the secondbuffer, the third buffer, and the fourth buffer beginning from the backof the space block 160. Then the first input unit 141 reads the firstbit data (assumed as “4” in the figures) of the fifth column of serialdata, and meanwhile the second input unit 142 also reads the first bitdata (assumed as “5” in the figures) of the sixth column of serial data,and then the data are temporarily stored in the fifth buffer and thesixth buffer at the back end of the space block 160.

Finally, the storing result is shown in FIG. 5 i, wherein the firstbuffer stores the first column of serial data, the second buffer storesthe second column of serial data, the third buffer stores the thirdcolumn of serial data, the fourth buffer stores the fourth column ofserial data, the fifth buffer stores the fifth column of serial data,and the sixth buffer stores the sixth column of serial data, and the 9×6blocks in the operating area 180 are fully occupied. In addition to fillthe first buffer, the second buffer, the third buffer, and the fourthbuffer, the first column of serial data, the second column of serialdata, the third column of serial data, and the fourth column of serialdata enable the individual remaining data to be stored in the firstmemory, the second memory, the third memory, and the fourth memorysequentially.

Then, the 9×5 tables 110 required for calculating EET are started to betaken out, as shown in FIG. 6. The first five columns of the 9x6 blocksare taken as the first 9×5 table 111, and the first central pixel 131(at the third column and fifth row of the 9×5 table) thereof is detectedto be a To Be Adjusted Pixel (TBAP) or not, and the second column to thesixth column of the 9×6 blocks are taken as the second 9×5 table 112,and the second central pixel 132 is detected in the table to be a TBAPor not. Supposing that the first central pixel 131 is determined to be aTBAP, it is calculated and adjusted with the first 9×5 table 111 throughone beam EET 10; similarly, when the second central pixel 132 is alsodetermined to be a TBAP, it is calculated and adjusted as well with thesecond 9×5 table 112 through one beam EET 10. But the central pixelswithout being adjusted can be directly transmitted to the LD, and outputto a display apparatus or a printing apparatus.

When the first column of serial data and the second column of serialdata both are removed as the operation has finished, the third column ofserial data and the fourth column of serial data in turn to fill thefirst buffer and the second buffer, and the fifth column of serial dataand the sixth column of serial data both have been read by the FIFObuffer 120 and SRAM 170 as well. All the serial data can be read andprocessed in a similar way.

Taking another embodiment as an example for illustration, referring toFIG. 7 a, supposing that in a digital image serial data 190, the first 4columns of serial data have already been adjusted through the EET, andat this time, the first central pixel 131 is a bit data at the fifthcolumn and the tenth row of the digital image serial data 190, and thesecond central pixel 132 is a bit data at the sixth column and the tenthrow of the digital image serial data 190. The Edge Enhancement operationis carried out to the 9×5 tables 111, 112 with the two TBAPs as thecentral pixels respectively, to obtain the adjusted pixel values, andthen to output the obtained values. Then, referring to FIG. 7 b, the twobit data to be removed after operation at the third column and the sixthrow and at the fourth column and the sixth row are removed from the FIFObuffer 120, while the remaining four bit data 182 in the same row arestored in one end of the SRAM 170. The next bit data of the first 4columns are captured from the other end of the SRAM 170 to be filled inthe end 184 of the first 4 buffers, while the next bit data read by thefirst read unit 141 and the second read unit 142 are stored at the end186 of the fifth and sixth buffers. Therefore, it can be seen clearlyfrom the figure that, the first central pixel 131 has replaced a with c,whereas the second central pixel 132 will also replace b with d, and thebit data in the two 9×5 tables 111, 112 are moved towards left by onebit, which is equivalent to the two 9×5 tables 111, 112 being movedtowards right by one bit with the next bit data of a and b as thecenter, and detected and adjusted through Edge Enhancement.

Referring to FIG. 8, it is a schematic view of carrying out EdgeEnhancement through extending the present invention to the multiple beampixel apparatus. And referring to FIG. 9, it is a flow chart of themethod of the present invention. First, the first column of serial datais read by the first input unit 141, and the second column of serialdata is read by the second input unit 142, and similarly, the n^(th)column of serial data is read by the n^(th) input unit 143. The first 9rows of data of the first buffer to the (n+4)^(th) buffer are filledaccording to the order of each column of the serial data, and those datain the first 4 columns of serial data without being stored in each ofthe buffers are temporarily stored in the SRAM 170 (step 100). Then,meanwhile n 9×5 tables 111, 112, . . . , 113 are taken out from the(n+4) buffers sequentially (step 200), for determining whether thecentral pixel 131, 132, . . . , 133 of each table is a To Be AdjustedPixel (TBAP) or not (step 300). If it is a TBAP, EET operation iscarried out to the 9×5 table with the TBAP as the central pixel, toobtain the adjusted central pixel value (step 400). Then, the n centralpixel values, being or without being adjusted, are output (step 500).Then the next bit data of the first n columns of serial data are read byeach input unit 141, 142, . . . , 143, and the read serial data in eachbuffer and SRAM 170 are moved (step 600), the details are shown in FIG.10. When the first input unit 141 to the n^(th) input unit 143 continuesto read the next bit data, the first rows of bit data of the firstbuffer to the n^(th) buffer are removed (step 610). And the first rowsof bit data of the (n+1)^(th) buffer to the (n+4)^(th) buffer are storedin one end of each of the first memory to the fourth memory (step 620).Each row of bit data behind the first row of the FIFO buffer 120 ismoved towards left by one bit (step 630). And a bit data is taken outfrom the other end of each of the 4 SRAMs 170, and they are sequentiallystored in the row at the end of the first buffer to the fourth buffer(step 640). The next bit data read by the first input unit 141 to then^(th) input unit 143 are stored in the fifth buffer to the (n+4)^(th)buffer (step 650). Finally, the central pixel value of each of the 9×5tables 111, 112, . . . , 113 is detected and adjusted according to theabove steps, until there is no next bit data to be output (step 700).

In summary, with the method disclosed in the present invention, each bitdata of the serial data to be processed by the Edge Enhancement willonly be read once by all the input units, thus there is no waste ofbandwidths for external output/input, and excessive processing resourcesof the central process unit (CPU) are not additionally required to readthe external data and the waiting time is not needed as well. And withthe method of the present invention, the demanding of FIFO buffer 120and SRAM 170 in the system will not increase by multiple times as thereare more and more input units 140 or a plurality of pixel outputs, andit will be controlled within a range increased by a constant. Therefore,the larger the number of the input units is, the more significantly theinternal resource consumption is reduced. And when reading n bit data, npixels processed by the EET can be output meanwhile, so long as theoperation capacity of the CPU is strong enough.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

1. A method for reducing memory consumption when carrying out EdgeEnhancement in a multiple beam pixel apparatus, applied to a multiplebeam pixel apparatus with n input units, the apparatus being providedwith (n+4) buffers and four static random access memories (SRAM), andthe first nine rows of the (n+4) buffers being an operation block; themethod comprising the following steps: filling the operation block withserial data sequentially, wherein as for the first four columns ofserial data in the operation block, since the first four buffers are allfully occupied, the serial data without being stored in each of thebuffers are temporarily stored in the four SRAMs; taking out n 9 by 5tables for detecting required by the Edge Enhancement according to thearranging order of each of the buffers in the operation block; carryingout the edge enhancement technology (EET) adjustment operation to thecentral pixels required to be edge enhanced in the n 9 by 5 tables;outputing the n central pixel values being adjusted or with no need ofbeing adjusted; moving the serial data having already been read by the(n+4) buffers and the four SRAMs; and reading the next bit data witheach of the n input units.
 2. The method for reducing memory consumptionwhen carrying out Edge Enhancement in a multiple beam pixel apparatusaccording to claim 1, wherein each of the buffers further comprises aregister block, for storing part of the serial data read by the n inputunits.
 3. The method for reducing memory consumption when carrying outEdge Enhancement in a multiple beam pixel apparatus according to claim2, wherein the register block is further used for storing the serialdata transferred from the four SRAMs due to moving.
 4. The method forreducing memory consumption when carrying out Edge Enhancement in amultiple beam pixel apparatus according to claim 2, wherein each of thebuffers further comprises a space block, for spacing the data of theregister block with the data of the operation block.
 5. The method forreducing memory consumption when carrying out Edge Enhancement in amultiple beam pixel apparatus according to claim 1, wherein each of thebuffers is a first in first out (FIFO) buffer.
 6. The method forreducing memory consumption when carrying out Edge Enhancement in amultiple beam pixel apparatus according to claim 1, wherein the centralpixel is the pixel at the third column and the fifth row of the 9 by 5table.
 7. The method for reducing memory consumption when carrying outEdge Enhancement in a multiple beam pixel apparatus according to claim1, wherein the first column of the n^(th) 9 by 5 table is the first ninerows of serial data of the n^(th) buffer, and the fifth column of then^(th) 9 by 5 table is the first nine rows of serial data of the(n+4)^(th) buffer.
 8. The method for reducing memory consumption whencarrying out Edge Enhancement in a multiple beam pixel apparatusaccording to claim 1, wherein moving the serial data having already beenread by the (n+4) buffers and the four SRAMs further comprises thefollowing steps: removing the first rows of bit data of the first bufferto the n^(th) buffer; storing the first rows of bit data of the(n+1)^(th) buffer to the (n+4)^(th) buffer in one end of each of thefour SRAMs; moving each row of bit data behind the first rows of thefirst buffer to the (n+4)^(th) buffer towards left by one bit; takingout a bit data from the other end of each of the four SRAMs, and storingthem sequentially in the row at the end of the first buffer to thefourth buffer; and storing the next bit data read by the first inputunit to the n^(th) input unit to the row at the end of the fifth bufferto the (n+4)^(th) buffer sequentially.
 9. A method for generating a nexttable by moving serial data, suitable for sequentially generating n 9 by5 tables for carrying out the EET operation when the first nine rows ofthe first buffer to the (n+4)^(th) buffer are all filled with the serialdata and the four SRAM have stored the serial data without being storedin each of the buffers, the method comprising the following steps:removing the first rows of bit data of the first buffer to the n^(th)buffer; storing the first rows of bit data of the (n+1)^(th) buffer tothe (n+4)^(th) buffer in one end of each of the four SRAMs; moving eachrow of bit data behind the first rows of the first buffer to the(n+4)^(th) buffer towards left by one bit; taking out a bit data fromthe other end of each of the four SRAMs, and storing them sequentiallyin the row at the end of the first buffer to the fourth buffer; andstoring the next bit data read by the first input unit to the n^(th)input unit to the row at the end of the fifth buffer to the (n+4)^(th)buffer sequentially.
 10. The method for generating a next table bymoving serial data according to claim 9, wherein the first column of then^(th) 9 by 5 table is the first nine rows of serial data of the n^(th)buffer, and the fifth column of the n^(th) 9 by 5 table is the firstnine rows of serial data of the (n+4)^(th) buffer.